Freescale Semiconductor MK22FN256VDC12, Reference Manual

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FTMx_COMBINE field descriptions (continued)
Field Description
24
COMBINE3
Combine Channels For n = 6
Enables the combine feature for channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 Channels (n) and (n+1) are independent.
1 Channels (n) and (n+1) are combined.
23
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
22
FAULTEN2
Fault Control Enable For n = 4
Enables the fault control in channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The fault control in this pair of channels is disabled.
1 The fault control in this pair of channels is enabled.
21
SYNCEN2
Synchronization Enable For n = 4
Enables PWM synchronization of registers C(n)V and C(n+1)V.
0 The PWM synchronization in this pair of channels is disabled.
1 The PWM synchronization in this pair of channels is enabled.
20
DTEN2
Deadtime Enable For n = 4
Enables the deadtime insertion in the channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The deadtime insertion in this pair of channels is disabled.
1 The deadtime insertion in this pair of channels is enabled.
19
DECAP2
Dual Edge Capture Mode Captures For n = 4
Enables the capture of the FTM counter value according to the channel (n) input event and the
configuration of the dual edge capture bits.
This field applies only when DECAPEN = 1.
DECAP bit is cleared automatically by hardware if dual edge capture – one-shot mode is selected and
when the capture of channel (n+1) event is made.
0 The dual edge captures are inactive.
1 The dual edge captures are active.
18
DECAPEN2
Dual Edge Capture Mode Enable For n = 4
Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit reconfigures the function of
MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in Dual Edge Capture mode according to
Table
38-7 .
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The Dual Edge Capture mode in this pair of channels is disabled.
1 The Dual Edge Capture mode in this pair of channels is enabled.
17
COMP2
Complement Of Channel (n) For n = 4
Table continues on the next page...
Memory map and register definition
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
844 Freescale Semiconductor, Inc.