The transmitter's LPUART_RTS signal asserts only when the transmitter is enabled.
However, the transmitter's LPUART_RTS signal is unaffected by its LPUART_CTS
signal. LPUART_RTS will remain asserted until the transfer is completed, even if the
transmitter is disabled mid-way through a data transfer.
47.3.3 Receiver functional description
In this section, the receiver block diagram is a guide for the overall receiver functional
description. Next, the data sampling technique used to reconstruct receiver data is
described in more detail. Finally, different variations of the receiver wakeup function are
explained.
The receiver input is inverted by setting LPUART_STAT[RXINV]. The receiver is
enabled by setting the LPUART_CTRL[RE] bit. Character frames consist of a start bit of
logic 0, eight to ten data bits (msb or lsb first), and one or two stop bits of logic 1. For
information about 9-bit or 10-bit data mode, refer to
8-bit, 9-bit and 10-bit data modes
.
For the remainder of this discussion, assume the LPUART is configured for normal 8-bit
data mode.
After receiving the stop bit into the receive shifter, and provided the receive data register
is not already full, the data character is transferred to the receive data register and the
receive data register full (LPUART_STAT[RDRF]) status flag is set. If
LPUART_STAT[RDRF] was already set indicating the receive data register (buffer) was
already full, the overrun (OR) status flag is set and the new data is lost. Because the
LPUART receiver is double-buffered, the program has one full character time after
LPUART_STAT[RDRF] is set before the data in the receive data buffer must be read to
avoid a receiver overrun.
When a program detects that the receive data register is full (LPUART_STAT[RDRF] =
1), it gets the data from the receive data register by reading LPUART_DATA. Refer to
for details about flag clearing.
47.3.3.1 Data sampling technique
The LPUART receiver supports a configurable oversampling rate of between 4× and 32×
of the baud rate clock for sampling. The receiver starts by taking logic level samples at
the oversampling rate times the baud rate to search for a falling edge on the
LPUART_RX serial data input pin. A falling edge is defined as a logic 0 sample after
three consecutive logic 1 samples. The oversampling baud rate clock divides the bit time
into 4 to 32 segments from 1 to OSR (where OSR is the configured oversampling ratio).
When a falling edge is located, three more samples are taken at (OSR/2), (OSR/2)+1, and
Functional description
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
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Freescale Semiconductor, Inc.
