Freescale Semiconductor MK22FN256VDC12, Reference Manual

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Clock Frequency
Bus clock 40 MHz
Flash clock 26.67 MHz
Option 3: High Speed Run
Clock Frequency
Core clock 120 MHz
System clock 120 MHz
Bus clock 60 MHz
Flash clock 24 MHz
5.5.1 Clock divider values after reset
Each clock divider is programmed via the SIM module’s CLKDIVn registers. The flash
memory's FTF_FOPT[LPBOOT] bit controls the reset value of the core clock, system
clock, bus clock, and flash clock dividers as shown below:
FTF_FOPT
[LPBOOT]
Core/system clock Bus clock Flash clock Description
0 0x7 (divide by 8) 0x7 (divide by 8) 0xF (divide by 16) Low power boot
1 0x0 (divide by 1) 0x0 (divide by 1) 0x1 (divide by 2) Fast clock boot
This gives the user flexibility for a lower frequency, low-power boot option. The flash
erased state defaults to fast clocking mode, since where the low power boot
(FTF_FOPT[LPBOOT]) bit resides in flash is logic 1 in the flash erased state.
To enable the low power boot option program FTF_FOPT[LPBOOT] to zero. During the
reset sequence, if LPBOOT is cleared, the system is in a slow clock configuration. Upon
any system reset, the clock dividers return to this configurable reset state.
5.5.2 VLPR mode clocking
The clock dividers cannot be changed while in VLPR mode. They must be programmed
prior to entering VLPR mode to guarantee:
• the core/system and bus clocks are less than or equal to 4 MHz, and
• the flash memory clock is less than or equal to 1 MHz
Chapter 5 Clock Distribution
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc. 153