receiver buffer level is less than RWFIFO[RXWATER]).
The C3 register needs to be read, prior to the D register,
only if the ninth bit of data needs to be captured. Similarly,
the ED register needs to be read, prior to the D register,
only if the additional flag data for the dataword needs to be
captured.
• In the normal 8-bit mode (M bit cleared) if the parity is
enabled, you get seven data bits and one parity bit. That
one parity bit is loaded into the D register. So, for the data
bits, mask off the parity bit from the value you read out of
this register.
• When transmitting in 9-bit data format and using 8-bit
write instructions, write first to transmit bit 8 in UART
control register 3 (C3[T8]), then D. A write to C3[T8]
stores the data in a temporary register. If D register is
written first, and then the new data on data bus is stored in
D, the temporary value written by the last write to C3[T8]
gets stored in the C3[T8] register.
Address: Base a 7h offset
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
UARTx_D field descriptions
Field
Description
7–0
RT
Reads return the contents of the read-only receive data register and writes go to the write-only transmit
data register.
46.3.9 UART Match Address Registers 1 (UARTx_MA1)
The MA1 and MA2 registers are compared to input data addresses when the most
significant bit is set and the associated C4[MAEN] field is set. If a match occurs, the
following data is transferred to the data register. If a match fails, the following data is
discarded. These registers can be read and written at anytime.
Address: Base a 8h offset
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
Memory map and registers
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
1150
Freescale Semiconductor, Inc.
