• DECAPEN = 0
• COMBINE = 0
• CPWMS = 0, and
• MSnB = 1
The EPWM period is determined by (MOD − CNTIN + 0x0001) and the pulse width
(duty cycle) is determined by (CnV − CNTIN).
The CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1 at the channel
(n) match (FTM counter = CnV), that is, at the end of the pulse width.
This type of PWM signal is called edge-aligned because the leading edges of all PWM
signals are aligned with the beginning of the period, which is the same for all channels
within an FTM.
period
counter overflow
counter overflow
counter overflow
channel (n) output
channel (n) match
channel (n) match
channel (n) match
pulse
width
Figure 38-182. EPWM period and pulse width with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = 0:0) when the counter reaches the value in the CnV register, the
CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1, however the
channel (n) output is not controlled by FTM.
If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the counter
overflow when the CNTIN register value is loaded into the FTM counter, and it is forced
low at the channel (n) match (FTM counter = CnV). See the following figure.
TOF bit
CHnF bit
CNT
channel (n) output
MOD = 0x0008
CnV = 0x0005
counter
overflow
channel (n)
match
counter
overflow
...
0
1
2
3
4
5
6
7
8
0
1
2
...
previous value
Figure 38-183. EPWM signal with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the counter
overflow when the CNTIN register value is loaded into the FTM counter, and it is forced
high at the channel (n) match (FTM counter = CnV). See the following figure.
Functional description
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
882
Freescale Semiconductor, Inc.
