44.4.2 Serial Peripheral Interface (SPI) configuration
The SPI configuration transfers data serially using a shift register and a selection of
programmable transfer attributes. The module is in SPI configuration when the DCONF
field in the MCR is 0b00. The SPI frames can be 32 bits long. The host CPU or a DMA
controller transfers the SPI data from the external to the module RAM queues to a TX
FIFO buffer. The received data is stored in entries in the RX FIFO buffer. The host CPU
or the DMA controller transfers the received data from the RX FIFO to memory external
to the module. The operation of FIFO buffers is described in the following sections:
•
Transmit First In First Out (TX FIFO) buffering mechanism
•
Transmit First In First Out (TX FIFO) buffering mechanism
•
Receive First In First Out (RX FIFO) buffering mechanism
The interrupt and DMA request conditions are described in
The SPI configuration supports two block-specific modes—Master mode and Slave
mode.In Master mode the module initiates and controls the transfer according to the
fields of the executing SPI Command. In Slave mode, the module responds only to
transfers initiated by a bus master external to it and the SPI command field space is
reserved.
44.4.2.1 Master mode
In SPI Master mode, the module initiates the serial transfers by controlling the SCK and
the PCS signals. The executing SPI Command determines which CTARs will be used to
set the transfer attributes and which PCS signals to assert. The command field also
contains various bits that help with queue management and transfer protocol. See
TX FIFO Register In Master Mode (SPI_PUSHR)
for details on the SPI command fields.
The data in the executing TX FIFO entry is loaded into the shift register and shifted out
on the Serial Out (SOUT) pin. In SPI Master mode, each SPI frame to be transmitted has
a command associated with it, allowing for transfer attribute control on a frame by frame
basis.
44.4.2.2 Slave mode
In SPI Slave mode the module responds to transfers initiated by an SPI bus master. It
does not initiate transfers. Certain transfer attributes such as clock polarity, clock phase,
and frame size must be set for successful communication with an SPI master. The SPI
Slave mode transfer attributes are set in the CTAR0. The data is shifted out with MSB
first. Shifting out of LSB is not supported in this mode.
Chapter 44 Serial Peripheral Interface (SPI)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
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