LPUARTx_CTRL field descriptions (continued)
Field
Description
0
Configures RWU for idle-line wakeup.
1
Configures RWU with address-mark wakeup.
2
ILT
Idle Line Type Select
Determines when the receiver starts counting logic 1s as idle character bits. The count begins either after
a valid start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding
the stop bit can cause false recognition of an idle character. Beginning the count after the stop bit avoids
false idle character recognition, but requires properly synchronized transmissions.
NOTE: In case the LPUART is programmed with ILT = 1, a logic 0 is automatically shifted after a
received stop bit, therefore resetting the idle count.
0
Idle character bit count starts after start bit.
1
Idle character bit count starts after stop bit.
1
PE
Parity Enable
Enables hardware parity generation and checking. When parity is enabled, the bit immediately before the
stop bit is treated as the parity bit.
0
No hardware parity generation or checking.
1
Parity enabled.
0
PT
Parity Type
Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total number
of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the
data character, including the parity bit, is even.
0
Even parity.
1
Odd parity.
Chapter 47 Low Power Universal asynchronous receiver/transmitter (LPUART)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
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