24.8.2 Refresh and unlock operations with 8-bit access
One exception condition that generates a reset to the system is the write of any value
other than those required for a legal refresh/update sequence to the respective refresh and
unlock registers.
For an 8-bit access to these registers, writing a correct value requires at least two bus
clock cycles, resulting in an invalid value in the registers for one cycle. Therefore, the
system is reset even if the intention is to write a correct value to the refresh/unlock
register. Keeping this in mind, the exception condition for 8-bit accesses is slightly
modified.
Whereas the match for a correct value for a refresh/unlock sequence is as according to the
original definition, the match for an incorrect value is done byte-wise on the refresh/
unlock rather than for the whole 16-bit value. This means that if the high byte of the
refresh/unlock register contains any value other than high bytes of the two values that
make up the sequence, it is treated as an exception condition, leading to a reset or
interrupt-then-reset. The same holds true for the lower byte of the refresh or unlock
register. Take the refresh operation that expects a write of 0xA602 followed by 0xB480
to the refresh register, as an example.
Table 24-14. Refresh for 8-bit access
WDOG_REFRESH[15:8]
WDOG_REFRESH[7:0]
Sequence value1 or
value2 match
Mismatch
exception
Current Value
0xB4
0x80
Value2 match
No
Write 1
0xB4
0x02
No match
No
Write 2
0xA6
0x02
Value1 match
No
Write 3
0xB4
0x02
No match
No
Write 4
0xB4
0x80
Value2 match.
Sequence complete.
No
Write 5
0x02
0x80
No match
Yes
As shown in the preceding table, the refresh register holds its reset value initially.
Thereafter, two 8-bit accesses are performed on the register to write the first value of the
refresh sequence. No mismatch exception is registered on the intermediate write, Write1.
The sequence is completed by performing two more 8-bit accesses, writing in the second
value of the sequence for a successful refresh. It must be noted that the match of value2
takes place only when the complete 16-bit value is correctly written, write4. Hence, the
requirement of writing value2 of the sequence within 20 bus clock cycles of value1 is
checked by measuring the gap between write2 and write4.
Watchdog operation with 8-bit access
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
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Freescale Semiconductor, Inc.
