The audio master clock generation and selection is chip-specific. Refer to chip-specific
clocking information about how the audio master clocks are generated. A typical
implementation appears in the following figure.
Fractional
Clock
Divider
1
0
11
01
10
00
EXTAL
PLL_OUT
ALT_CLK
SYS_CLK
SAI_MOE
MCLK
MCLK_OUT
MCLK_IN
11
01
10
00
BUS_CLK
SAI_CLKMODE
Bit
Clock
Divider
1
0
BCLK_IN
SAI
BCLK_OUT
SAI_BCD
BCLK
SAI_FRACT/SAI_DIVIDE
SAI_MICS
MCLK (other SAIs)
CLKGEN
Figure 48-50. SAI master clock generation
The MCLK fractional clock divider uses both clock edges from the input clock to
generate a divided down clock that will approximate the output frequency, but without
creating any new clock edges. Configuring FRACT and DIVIDE to the same value will
result in a divide by 1 clock, while configuring FRACT higher than DIVIDE is not
supported. The duty cycle can range from 66/33 when FRACT is set to one less than
DIVIDE down to 50/50 for integer divide ratios, and will approach 50/50 for large non-
integer divide ratios. There is no cycle to cycle jitter or duty cycle variance when the
divide ratio is an integer or half integer, otherwise the divider output will oscillate
between the two divided frequencies that are the closest integer or half integer divisors of
the divider input clock frequency. The maximum jitter is therefore equal to half the
divider input clock period, since both edges of the input clock are used in generating the
divided clock.
48.4.1.2 Bit clock
The SAI transmitter and receiver support asynchronous free-running bit clocks that can
be generated internally from an audio master clock or supplied externally. There is also
the option for synchronous bit clock and frame sync operation between the receiver and
transmitter or between multiple SAI peripherals.
Externally generated bit clocks must be:
• Enabled before the SAI transmitter or receiver is enabled
• Disabled after the SAI transmitter or receiver is disabled and completes its current
frames
Functional description
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
1280
Freescale Semiconductor, Inc.
