32.4.2 Core engine / control logic
This block contains RNGA's control logic as well as its core engine used to generate
random data.
32.4.2.1 Control logic
The control logic contains the address decoder, all addressable registers, and control state
machines for RNGA. This block is responsible for communication with both the
peripheral interface and the Output (OR) register interface. The block also controls the
core engine to generate random data. The general functionality of the block is as follows:
After reset, RNGA operates in Normal mode as follows:
1. The core engine generates entropy and stores it in the shift registers.
2. After you enable random-data generation by loading CR[GO], every 256 clock
cycles the core engine generates a new random-data word. If SR[OREG_LVL] = 0,
then the control block loads the new random data into OR and set SR[OREG_LVL]
= 1; else the new data is discarded.
32.4.2.2 Core engine
The core engine block contains the logic used to generate random data. The logic within
the core engine contains the internal shift registers as well as the logic used to generate
the two oscillator-based clocks. The control logic determines how the shift registers are
configured as well as when the oscillator clocks are turned on.
32.5 Initialization/application information
The intended general operation of RNGA is as follows:
1. Reset/initialize.
2. Write 1 to CR[INTM], CR[HA], and CR[GO].
3. Poll SR[OREG_LVL] until it is not 0.
4. When SR[OREG_LVL] is not 0, read the available random data from
OR[RANDOUT].
5. Repeat steps 3 and 4 as needed.
Chapter 32 Random Number Generator Accelerator (RNGA)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
689
