Freescale Semiconductor MK22FN256VDC12, Reference Manual

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The conversion time for a single conversion is calculated by using the Figure 33-92 , and
the information provided in Table 33-104 through Table 33-108 . The table below lists the
variables of Figure 33-92 .
Table 33-109. Typical conversion time
Variable Time
SFCAdder 5 ADCK 5 bus clock cycles
AverageNum 1
BCT 20 ADCK cycles
LSTAdder 0
HSCAdder 0
The resulting conversion time is generated using the parameters listed in the preceding
table. Therefore, for a bus clock and an ADCK frequency equal to 8 MHz, the resulting
conversion time is 3.75 µs.
33.4.4.6.2 Long conversion time configuration
A configuration for long ADC conversion is:
• 16-bit differential mode with the bus clock selected as the input clock source
• The input clock divide-by-8 ratio selected
• Bus frequency of 8 MHz
• Long sample time enabled
• Configured for longest adder
• High-speed conversion disabled
• Average enabled for 32 conversions
The conversion time for this conversion is calculated by using the Figure 33-92 , and the
information provided in Table 33-104 through Table 33-108 . The following table lists the
variables of the Figure 33-92 .
Table 33-110. Typical conversion time
Variable Time
SFCAdder 3 ADCK 5 bus clock cycles
AverageNum 32
BCT 34 ADCK cycles
LSTAdder 20 ADCK cycles
HSCAdder 0
Functional description
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
726 Freescale Semiconductor, Inc.