22.3.4 Reserved memory and bit fields
• Reading reserved bits in a register returns the value of zero.
• Writes to reserved bits in a register are ignored.
• Reading or writing a reserved memory location generates a bus error.
DMA memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_8000 Control Register (DMA_CR)
32
R/W
0000_0000h
4000_8004 Error Status Register (DMA_ES)
32
R
0000_0000h
4000_800C Enable Request Register (DMA_ERQ)
32
R/W
0000_0000h
4000_8014 Enable Error Interrupt Register (DMA_EEI)
32
R/W
0000_0000h
4000_8018 Clear Enable Error Interrupt Register (DMA_CEEI)
8
W
(always
reads 0)
00h
4000_8019 Set Enable Error Interrupt Register (DMA_SEEI)
8
W
(always
reads 0)
00h
4000_801A Clear Enable Request Register (DMA_CERQ)
8
W
(always
reads 0)
00h
4000_801B Set Enable Request Register (DMA_SERQ)
8
W
(always
reads 0)
00h
4000_801C Clear DONE Status Bit Register (DMA_CDNE)
8
W
(always
reads 0)
00h
4000_801D Set START Bit Register (DMA_SSRT)
8
W
(always
reads 0)
00h
4000_801E Clear Error Register (DMA_CERR)
8
W
(always
reads 0)
00h
4000_801F Clear Interrupt Request Register (DMA_CINT)
8
W
(always
reads 0)
00h
4000_8024 Interrupt Request Register (DMA_INT)
32
R/W
0000_0000h
4000_802C Error Register (DMA_ERR)
32
R/W
0000_0000h
4000_8034 Hardware Request Status Register (DMA_HRS)
32
R
0000_0000h
4000_8044
Enable Asynchronous Request in Stop Register
(DMA_EARS)
32
R/W
0000_0000h
4000_8100 Channel n Priority Register (DMA_DCHPRI3)
8
R/W
4000_8101 Channel n Priority Register (DMA_DCHPRI2)
8
R/W
4000_8102 Channel n Priority Register (DMA_DCHPRI1)
8
R/W
Table continues on the next page...
Memory map/register definition
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
424
Freescale Semiconductor, Inc.
