CMPx_CR1 field descriptions (continued)
Field
Description
0
Analog Comparator is disabled.
1
Analog Comparator is enabled.
34.2.3 CMP Filter Period Register (CMPx_FPR)
Address: Base a 2h offset
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
CMPx_FPR field descriptions
Field
Description
7–0
FILT_PER
Filter Sample Period
Specifies the sampling period, in bus clock cycles, of the comparator output filter, when CR1[SE]=0.
Setting FILT_PER to 0x0 disables the filter. Filter programming and latency details appear in the
.
This field has no effect when CR1[SE]=1. In that case, the external SAMPLE signal is used to determine
the sampling period.
34.2.4 CMP Status and Control Register (CMPx_SCR)
Address: Base a 3h offset
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
CMPx_SCR field descriptions
Field
Description
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6
DMAEN
DMA Enable Control
Enables the DMA transfer triggered from the CMP module. When this field is set, a DMA request is
asserted when CFR or CFF is set.
0
DMA is disabled.
1
DMA is enabled.
Table continues on the next page...
Chapter 34 Comparator (CMP)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
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