of the module is empty, and a transfer is initiated from an external SPI master. If the
TFUF bit is set while the TFUF_RE bit in the RSER is set, an interrupt request is
generated.
44.4.7.5 Receive FIFO Drain Interrupt or DMA Request
The Receive FIFO Drain Request indicates that the RX FIFO is not empty. The Receive
FIFO Drain Request is generated when the number of entries in the RX FIFO is not zero,
and the RFDF_RE bit in the RSER is set. The RFDF_DIRS bit in the RSER selects
whether a DMA request or an interrupt request is generated.
44.4.7.6 Receive FIFO Overflow Interrupt Request
The Receive FIFO Overflow Request indicates that an overflow condition in the RX
FIFO has occurred. A Receive FIFO Overflow request is generated when RX FIFO and
shift register are full and a transfer is initiated. The RFOF_RE bit in the RSER must be
set for the interrupt request to be generated.
Depending on the state of the ROOE bit in the MCR, the data from the transfer that
generated the overflow is either ignored or shifted in to the shift register. If the ROOE bit
is set, the incoming data is shifted in to the shift register. If the ROOE bit is cleared, the
incoming data is ignored.
44.4.8 Power saving features
The module supports following power-saving strategies:
• External Stop mode
• Module Disable mode – Clock gating of non-memory mapped logic
44.4.8.1 Stop mode (External Stop mode)
This module supports the Stop mode protocol. When a request is made to enter External
Stop mode, the module acknowledges the request . If a serial transfer is in progress, then
this module waits until it reaches the frame boundary before it is ready to have its clocks
shut off . While the clocks are shut off, this module's memory-mapped logic is not
Chapter 44 Serial Peripheral Interface (SPI)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
1087
