PDBx_POEN field descriptions (continued)
Field
Description
0
PDB Pulse-Out disabled
1
PDB Pulse-Out enabled
37.3.12 Pulse-Out n Delay register (PDBx_POnDLY)
Address: 4003_6000h base + 194h (4d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_POnDLY field descriptions
Field
Description
31–16
DLY1
PDB Pulse-Out Delay 1
Specifies the delay 1 value for the PDB Pulse-Out. Pulse-Out goes high when the PDB counter is equal to
the DLY1. Reading this field returns the value of internal register that is effective for the current PDB cycle.
15–0
DLY2
PDB Pulse-Out Delay 2
Specifies the delay 2 value for the PDB Pulse-Out. Pulse-Out goes low when the PDB counter is equal to
the DLY2. Reading this field returns the value of internal register that is effective for the current PDB cycle.
37.4 Functional description
37.4.1 PDB pre-trigger and trigger outputs
The PDB contains a counter whose output is compared to several different digital values.
If the PDB is enabled, then a trigger input event will reset the counter and make it start to
count. A trigger input event is defined as a rising edge being detected on a selected
trigger input source, or if a software trigger is selected and SC[SWTRIG] is written with
1. For each channel, a delay m determines the time between assertion of the trigger input
event to the time at which changes in the pre-trigger m output signal are started. The time
is defined as:
Chapter 37 Programmable Delay Block (PDB)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
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