LPUART0 clock
IRC48MCLK
SIM_SOPT2[LPUARTSRC]
SIM_SOPT2[PLLFLLSEL]
MCGFLLCLK
MCGIRCLK
OSCERCLK
MCGPLLCLK
Figure 5-8. LPUART0 clock generation
5.7.11 I
2
S/SAI clocking
The audio master clock (MCLK) is used to generate the bit clock when the receiver or
transmitter is configured for an internally generated bit clock. The audio master clock can
also be output to or input from a pin. The transmitter and receiver have the same audio
master clock inputs.
Each SAI peripheral can control the input clock selection, pin direction and divide ratio
of one audio master clock.
The I
2
S/SAI transmitter and receiver support asynchronous bit clocks (BCLKs) that can
be generated internally from the audio master clock or supplied externally. The module
also supports the option for synchronous operation between the receiver and transmitter
product.
The transmitter and receiver can independently select between the bus clock and the
audio master clock to generate the bit clock.
The MCLK and BCLK source options appear in the following figure.
Module clocks
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
162
Freescale Semiconductor, Inc.
