SPIx_MCR field descriptions (continued)
Field
Description
1
Reserved
This field is reserved.
0
HALT
Halt
The HALT bit starts and stops frame transfers. See
Start and Stop of Module transfers
0
Start transfers.
1
Stop transfers.
44.3.2 Transfer Count Register (SPIx_TCR)
TCR contains a counter that indicates the number of SPI transfers made. The transfer
counter is intended to assist in queue management. Do not write the TCR when the
module is in the Running state.
Address: Base a 8h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPIx_TCR field descriptions
Field
Description
31–16
SPI_TCNT
SPI Transfer Counter
Counts the number of SPI transfers the module makes. The SPI_TCNT field increments every time the
last bit of an SPI frame is transmitted. A value written to SPI_TCNT presets the counter to that value.
SPI_TCNT is reset to zero at the beginning of the frame when the CTCNT field is set in the executing SPI
command. The Transfer Counter wraps around; incrementing the counter past 65535 resets the counter to
zero.
15–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
44.3.3 Clock and Transfer Attributes Register (In Master Mode)
(SPIx_CTARn)
CTAR registers are used to define different transfer attributes. Do not write to the CTAR
registers while the module is in the Running state.
Chapter 44 Serial Peripheral Interface (SPI)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
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