48.3.5 SAI Transmit Configuration 4 Register (I2Sx_TCR4)
This register must not be altered when TCSR[TE] is set.
Address: 4002_F000h base + 10h offset = 4002_F010h
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I2Sx_TCR4 field descriptions
Field
Description
31–29
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
28
FCONT
FIFO Continue on Error
Configures when the SAI will continue transmitting after a FIFO error has been detected.
0
On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been
cleared.
1
On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the
FIFO warning flag has been cleared.
27–26
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
25–24
FPACK
FIFO Packing Mode
Enables packing of 8-bit data or 16-bit data into each 32-bit FIFO word. If the word size is greater than 8-
bit or 16-bit then only the first 8-bit or 16-bits are loaded from the FIFO. The first word in each frame
always starts with a new 32-bit FIFO word and the first bit shifted must be configured within the first
packed word. When FIFO packing is enabled, the FIFO write pointer will only increment when the full 32-
bit FIFO word has been written by software.
00
FIFO packing is disabled
01
Reserved
10
8-bit FIFO packing is enabled
11
16-bit FIFO packing is enabled
23–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Memory map and register definition
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
1262
Freescale Semiconductor, Inc.
