Table 23-8. EWM Refresh Mechanisms
Condition
Mechanism
A unique EWM service occurs when CMPL
< Counter < CMPH.
The software behaves as expected and the counter of the EWM is reset to zero,
and EWM_out pin remains in the deasserted state.
Note: EWM_in pin is also assumed to be in the deasserted state.
A unique EWM service occurs when
Counter < CMPL
The software services the EWM and therefore resets the counter to zero and
asserts the EWM_out pin (irrespective of the EWM_in pin). The EWM_out pin is
expected to gate critical safety circuits.
Counter value reaches CMPH prior to a
unique EWM service
The counter value reaches the CMPH value and no service of the EWM resets
the counter to zero and assert the EWM_out pin (irrespective of the EWM_in
pin). The EWM_out pin is expected to gate critical safety circuits.
Any illegal service on EWM has no effect on EWM_out.
23.4.6 EWM Interrupt
When EWM_out is asserted, an interrupt request is generated to indicate the assertion of
the EWM reset out signal. This interrupt is enabled when CTRL[INTEN] is set. Clearing
this bit clears the interrupt request but does not affect EWM_out. The EWM_out signal
can be deasserted only by forcing a system reset.
23.4.7 Counter clock prescaler
The EWM counter clock source can be prescaled by a clock divider, by programming
CLKPRESCALER[CLK_DIV]. This divided clock is used to run the EWM counter.
NOTE
The divided clock used to run the EWM counter must be no
more than half the frequency of the bus clock.
Functional Description
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
510
Freescale Semiconductor, Inc.
