SPIx_RSER field descriptions (continued)
Field
Description
14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
44.3.7 PUSH TX FIFO Register In Master Mode (SPIx_PUSHR)
Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access transfers all
32 bits to the TX FIFO. In Master mode, the register transfers 16 bits of data and 16 bits
of command information.In Slave mode, all 32 bits can be used as data, supporting up to
32-bit frame operation.
A read access of PUSHR returns the topmost TX FIFO entry.
When the module is disabled, writing to this register does not update the FIFO.
Therefore, any reads performed while the module is disabled return the last PUSHR write
performed while the module was still enabled.
Address: Base a 34h offset
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPIx_PUSHR field descriptions
Field
Description
31
CONT
Continuous Peripheral Chip Select Enable
Selects a continuous selection format. The bit is used in SPI Master mode. The bit enables the selected
PCS signals to remain asserted between transfers.
0
Return PCSn signals to their inactive state between transfers.
1
Keep PCSn signals asserted between transfers.
Table continues on the next page...
Chapter 44 Serial Peripheral Interface (SPI)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
1065
