Atmel ATSAML22G16A-AUT, Manual

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26.9. Register Summary - SRAM
Offset Name Bit Pos.
0x00
BTCTRL
7:0 BLOCKACT[1:0] EVOSEL[1:0] VALID
0x01 15:8 STEPSIZE[2:0] STEPSEL DSTINC SRCINC BEATSIZE[1:0]
0x02
BTCNT
7:0 BTCNT[7:0]
0x03 15:8 BTCNT[15:8]
0x04
SRCADDR
7:0 SRCADDR[7:0]
0x05 15:8 SRCADDR[15:8]
0x06 23:16 SRCADDR[23:16]
0x07 31:24 SRCADDR[31:24]
0x08
DSTADDR
7:0 DSTADDR[7:0]
0x09 15:8 DSTADDR[15:8]
0x0A 23:16 DSTADDR[23:16]
0x0B 31:24 DSTADDR[31:24]
0x0C
DESCADDR
7:0 DESCADDR[7:0]
0x0D 15:8 DESCADDR[15:8]
0x0E 23:16 DESCADDR[23:16]
0x0F 31:24 DESCADDR[31:24]
26.10. Register Description - SRAM
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write-protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to
Register Access Protection .
Some registers are enable-protected, meaning they can only be written when the peripheral is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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