The I/O pins of the device are controlled by PORT peripheral registers. Each port pin has a corresponding
bit in the Data Direction (DIR) and Data Output Value (OUT) registers to enable that pin as an output and
to define the output state.
The direction of each pin in a PORT group is configured by the DIR register. If a bit in DIR is set to '1', the
corresponding pin is configured as an output pin. If a bit in DIR is set to '0', the corresponding pin is
configured as an input pin.
When the direction is set as output, the corresponding bit in the OUT register will set the level of the pin. If
bit y in OUT is written to '1', pin y is driven HIGH. If bit y in OUT is written to '0', pin y is driven LOW. Pin
configuration can be set by Pin Configuration (PINCFGy) registers, with y=00, 01, ..31 representing the
bit position.
The Data Input Value (IN) is set as the input value of a port pin with resynchronization to the PORT clock.
To reduce power consumption, these input synchronizers are clocked only when system requires reading
the input value. The value of the pin can always be read, whether the pin is configured as input or output.
If the Input Enable bit in the Pin Configuration registers (PINCFGy.INEN) is '0', the input value will not be
sampled.
In PORT, the Peripheral Multiplexer Enable bit in the PINCFGy register (PINCFGy.PMUXEN) can be
written to '1' to enable the connection between peripheral functions and individual I/O pins. The Peripheral
Multiplexing n (PMUXn) registers select the peripheral function for the corresponding pin. This will
override the connection between the PORT and that I/O pin, and connect the selected peripheral signal to
the particular I/O pin instead of the PORT line bundle.
29.6.2. Basic Operation
29.6.2.1. Initialization
After reset, all standard function device I/O pads are connected to the PORT with outputs tri-stated and
input buffers disabled, even if there is no clock running.
However, specific pins, such as those used for connection to a debugger, may be configured differently,
as required by their special function.
29.6.2.2. Operation
Each I/O pin y can be controlled by the registers in PORT. Each PORT group has its own set of PORT
registers, the base address of the register set for pin y is at byte address PORT + ([y] * 0x4). The index
within that register set is [y].
To use pin number y as an
output
, write bit y of the DIR register to '1'. This can also be done by writing bit
y in the DIRSET register to '1' - this will avoid disturbing the configuration of other pins in that group. The
y bit in the OUT register must be written to the desired output value.
Similarly, writing an OUTSET bit to '1' will set the corresponding bit in the OUT register to '1'. Writing a bit
in OUTCLR to '1' will set that bit in OUT to zero. Writing a bit in OUTTGL to '1' will toggle that bit in OUT.
To use pin y as an
input
, bit y in the DIR register must be written to '0'. This can also be done by writing
bit y in the DIRCLR register to '1' - this will avoid disturbing the configuration of other pins in that group.
The input value can be read from bit y in register IN as soon as the INEN bit in the Pin Configuration
register (PINCFGy.INEN) is written to '1'.
Refer to
I/O Multiplexing and Considerations
for details on pin configuration and PORT groups.
By default, the input synchronizer is clocked only when an input read is requested. This will delay the
read operation by two CLK_PORT cycles. To remove the delay, the input synchronizers for each PORT
group of eight pins can be configured to be always active, but this will increase power consumption. This
Atmel SAM L22G / L22J / L22N [DATASHEET]
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