Figure 26-5. Static Priority Scheduling
Highest Channel
Lowest Channel
Highest Priority
Lowest Priority
Channel N
Channel 0
Channel x+1
Channel x
.
.
.
.
.
.
Dynamic Arbitration
within a priority level is selected by writing a '1' to
.RRLVLENx.
The dynamic arbitration scheme in the DMAC is round-robin. With the round-robin scheme, the channel
number of the last channel being granted access will have the lowest priority the next time the arbiter has
to grant access to a channel within the same priority level, as shown in
. The channel number
of the last channel being granted access as the active channel is stored in the Level x Channel Priority
Number bit group in the Priority Control 0 register (
.LVLPRIx) for the corresponding priority
level.
Figure 26-6. Dynamic (Round-Robin) Priority Scheduling
Channel N
Channel N
Channel 0
Channel x
Channel x+1
Channel x last acknowledge request
Channel (x+1) last acknowledge request
Channel 0
Channel x
Channel x+1
Channel x+2
Lowest Priority
Highest Priority
Highest Priority
Lowest Priority
.
.
.
.
.
.
26.6.2.5. Data Transmission
Before the DMAC can perform a data transmission, a DMA channel has to be configured and enabled, its
corresponding transfer descriptor has to be initialized, and the arbiter has to grant the DMA channel
access as the active channel.
Once the arbiter has granted a DMA channel access as the active channel (refer to
transfer descriptor for the DMA channel will be fetched from SRAM using the fetch bus, and stored in the
Atmel SAM L22G / L22J / L22N [DATASHEET]
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