Atmel ATSAML22G16A-AUT, Manual

Page: 480 / 1231

26.8.19. Channel Control B
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Name: CHCTRLB
Offset: 0x44
Reset: 0x00000000
Property:
PAC Write-Protection, Enable-Protected
Bit 31 30 29 28 27 26 25 24
CMD[1:0]
Access R/W R/W
Reset 0 0
Bit 23 22 21 20 19 18 17 16
TRIGACT[1:0]
Access R/W R/W
Reset 0 0
Bit 15 14 13 12 11 10 9 8
TRIGSRC[5:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
LVL[1:0] EVOE EVIE EVACT[2:0]
Access R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bits 25:24 – CMD[1:0]: Software Command
These bits define the software commands. Refer to Channel Suspend and Channel Resume and Next
Suspend Skip .
These bits are not enable-protected.
CMD[1:0] Name Description
0x0 NOACT No action
0x1 SUSPEND Channel suspend operation
0x2 RESUME Channel resume operation
0x3 - Reserved
Bits 23:22 – TRIGACT[1:0]: Trigger Action
These bits define the trigger action used for a transfer.
TRIGACT[1:0] Name Description
0x0 BLOCK One trigger required for each block transfer
0x1 - Reserved
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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