28.5.6. Analog Connections
Not applicable.
28.6. Functional Description
28.6.1. Principle of Operation
The NVM Controller is a slave on the AHB and APB buses. It responds to commands, read requests and
write requests, based on user configuration.
28.6.1.1. Initialization
After power up, the NVM Controller goes through a power-up sequence. During this time, access to the
NVM Controller from the AHB bus is halted. Upon power-up completion, the NVM Controller is
operational without any need for user configuration.
28.6.2. Memory Organization
Refer to the Physical Memory Map for memory sizes and addresses for each device.
The NVM is organized into rows, where each row contains four pages, as shown in the NVM Row
Organization figure. The NVM has a row-erase granularity, while the write granularity is by page. In other
words, a single row erase will erase all four pages in the row, while four write operations are used to write
the complete row.
Figure 28-2. NVM Row Organization
Page (n*4) + 3
Page (n*4) + 2
Page (n*4) + 1
Page (n*4) + 0
Row n
The NVM block contains a calibration and auxiliary space plus a dedicated EEPROM emulation space
that are memory mapped. Refer to the NVM Organization figure below for details.
The calibration and auxiliary space contains factory calibration and system configuration information.
These spaces can be read from the AHB bus in the same way as the main NVM main address space.
In addition, a boot loader section can be allocated at the beginning of the main array, and an EEPROM
section can be allocated at the end of the NVM main address space.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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