Atmel ATSAML22G16A-AUT, Manual

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21.8.15. DPLL Control B
Name: DPLLCTRLB
Offset: 0x30
Reset: 0x00
Property:
Enable-Protected, PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
DIV[10:8]
Access R/W R/W R/W
Reset 0 0 0
Bit 23 22 21 20 19 18 17 16
DIV[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
LBYPASS LTIME[2:0]
Access R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
REFCLK[1:0] WUF LPEN FILTER[1:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 26:16 – DIV[10:0]: Clock Divider
These bits set the XOSC clock division factor and can be calculated with following formula:
f
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=
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2� ��� + 1
Bit 12 – LBYPASS: Lock Bypass
Value Description
0 DPLL Lock signal drives the DPLL controller internal logic.
1 DPLL Lock signal is always asserted.
Bits 10:8 – LTIME[2:0]: Lock Time
These bits select the lock time-out value:
Value Name Description
0x0 Default No time-out. Automatic lock.
0x1 Reserved
0x2 Reserved
0x3 Reserved
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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