Figure 14-6. DATA bits Description When MBIST Operation Returns an Error
Bit
Bit
Bit
Bit
phase
bit_index
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
•
bit_index: contains the bit number of the failing bit
•
phase: indicates which phase of the test failed and the cause of the error, as listed in the following
table.
Table 14-4. MBIST Operation Phases
Phase
Test actions
0
Write all bits to zero. This phase cannot fail.
1
Read '0', write '1', increment address
2
Read '1', write '0'
3
Read '0', write '1', decrement address
4
Read '1', write '0', decrement address
5
Read '0', write '1'
6
Read '1', write '0', decrement address
7
Read all zeros. bit_index is not used
Table 14-5. AMOD Bit Descriptions for MBIST
AMOD[1:0]
Description
0x0
Exit on Error
0x1
Pause on Error
0x2, 0x3
Reserved
Related Links
NVMCTRL – Non-Volatile Memory Controller
on page 515
on page 523
14.11.6. System Services Availability when Accessed Externally
External access: Access performed in the DSU address offset 0x200-0x1FFF range.
Internal access: Access performed in the DSU address offset 0x0-0x100 range.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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