When the even LUT is disabled (LUTCTRL2x.ENABLE=0), the latch output will be cleared. The G-input is
forced enabled for one more APB clock cycle, and the D-input to zero. In all other cases, the latch output
(OUT) is refreshed as shown in
.
Table 40-4. D-Latch Characteristics
G
D
OUT
0
X
Hold state (no change)
1
0
Clear
1
1
Set
RS Latch (RS)
When this configuration is selected, the S-input is driven by the even LUT output (LUT2x), and the R-
input is driven by the odd LUT output (LUT2x+1), as shown in
Figure 40-17. RS-Latch
RS-latch
S
Q
R
LUT2x
LUT(2x+1)
OUT
When the even LUT is disabled (LUTCTRL2x.ENABLE=0), the latch output will be cleared. The R-input is
forced enabled for one more APB clock cycle and S-input to zero. In all other cases, the latch output
(OUT) is refreshed as shown in
.
Table 40-5. RS-latch Characteristics
S
R
OUT
0
0
Hold state (no change)
0
1
Clear
1
0
Set
1
1
Forbidden state
40.6.3. Events
The CCL can generate the following output events:
•
LUTOUTx: Lookup Table Output Value
Writing a '1' to the LUT Control Event Output Enable bit (LUTCTRL.LUTEO) enables the corresponding
output event. Writing a '0' to this bit disables the corresponding output event. Refer to
EVSYS – Event
System
for details on configuration.
The CCL can take the following actions on an input event:
•
INx: The event is used as input for the TRUTH table. For further details refer to
Writing a '1' to the LUT Control Event Input Enable bit (LUTCTRL.LUTEI) enables the corresponding
action on input event. Writing a '0' to this bit disables the corresponding action on input event. Refer to
EVSYS – Event System
for details on configuration.
Related Links
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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