•
Result Conversion Ready (RESRDY): the request is set when a conversion result is available and
cleared when the RESULT register is read. When the averaging operation is enabled, the DMA
request is set when the averaging is completed and result is available.
41.6.4. Interrupts
The ADC has the following interrupt sources:
•
Result Conversion Ready: RESRDY
•
Window Monitor: WINMON
•
Overrun: OVERRUN
These interrupts are asynchronous wake-up sources. See
Sleep Mode Controller
for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually
enabled by writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and
disabled by writing a one to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An
interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the ADC
is reset. See
for details on how to clear interrupt flags. All interrupt requests from the peripheral
are ORed together on system level to generate one combined interrupt request to the NVIC. Refer to
Nested Vector Interrupt Controller
for details. The user must read the INTFLAG register to determine
which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to
Nested
Vector Interrupt Controller
for details.
Related Links
Nested Vector Interrupt Controller
on page 44
on page 191
41.6.5. Events
The ADC can generate the following output events:
•
Result Ready (RESRDY): Generated when the conversion is complete and the result is available.
Refer to
•
Window Monitor (WINMON): Generated when the window monitor condition match. Refer to
Setting an Event Output bit in the Event Control Register (EVCTRL.xxEO=1) enables the corresponding
output event. Clearing this bit disables the corresponding output event. Refer to the Event System
chapter for details on configuring the event system.
The ADC can take the following actions on an input event:
•
Start conversion (START): Start a conversion. Refer to
for details.
•
Conversion flush (FLUSH): Flush the conversion. Refer to
Setting an Event Input bit in the Event Control register (EVCTRL.xxEI=1) enables the corresponding
action on input event. Clearing this bit disables the corresponding action on input event.
The ADC uses only asynchronous events, so the asynchronous Event System channel path must be
configured. By default, the ADC will detect a rising edge on the incoming event. If the ADC action must be
performed on the falling edge of the incoming event, the event line must be inverted first. This is done by
setting the corresponding Event Invert Enable bit in Event Control register (EVCTRL.xINV=1).
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
998
