43.5.2. Power Management
The SLCD will continue to operate in any sleep mode where the selected source clock is running. The
SLCD interrupts can be used to wake up the device from sleep modes. Events connected to the event
system can trigger other operations in the system without exiting sleep modes.
Related Links
43.5.3. Clocks
The SLCD bus clock (CLK_SLCD_APB) can be enabled and disabled in the Main Clock module MCLK,
and the default state of CLK_SLCD_APB can be found in Peripheral Clock Masking section.
A 32.768kHz oscillator clock (CLK_SLCD_OSC) is required to clock the SLCD. This clock must be
configured and enabled in the 32KHz oscillator controller (OSC32KCTRL) before using the SLCD.
This oscillator clock is asynchronous to the bus clock (CLK_SLCD_APB). Due to this asynchronicity,
writes to certain registers will require synchronization between the clock domains.
Related Links
on page 145
OSC32KCTRL – 32KHz Oscillators Controller
on page 258
on page 264
Synchronous and Asynchronous Clocks
on page 116
43.5.4. DMA
The DMA request lines are connected to the DMA Controller (DMAC). Using the SLCD DMA requests
requires the DMA Controller to be configured first.
Related Links
DMAC – Direct Memory Access Controller
on page 432
43.5.5. Interrupts
The interrupt request line is connected to the interrupt controller. Using the SLCD interrupt(s) requires the
interrupt controller to be configured first.
43.5.6. Events
The events are connected to the Event System.
Related Links
43.5.7. Debug Operation
When the CPU is halted in debug mode the SLCD continues normal operation. If the SLCD is configured
in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper
operation or data loss may result during debugging.
43.5.8. Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller
(PAC), except the following registers:
•
Interrupt Flag Status and Clear register (INTFLAG)
•
Segments Data Low and High for COMx Line (SDATAL/Hx)
•
Indirect Segments Data Access (ISDATA)
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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