32.8.9. Status
Name:
STATUS
Offset:
0x1A
Reset:
0x0000
Property:
-
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
ITER
COLL
ISF
CTS
BUFOVF
FERR
PERR
Access
R/W
R/W
R/W
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Bit 6 – ITER: Maximum Number of Repetitions Reached
This bit is set when the maximum number of NACK repetitions or retransmissions is met in ISO7816 T=0
mode.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Bit 5 – COLL: Collision Detected
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set when collision detection is enabled (CTRLB.COLDEN) and a collision is detected.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Bit 4 – ISF: Inconsistent Sync Field
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set when the frame format is set to auto-baud (CTRLA.FORM) and a sync field not equal to
0x55 is received.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear it.
Bit 3 – CTS: Clear to Send
This bit indicates the current level of the CTS pin when flow control is enabled (CTRLA.TXPO).
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
Bit 2 – BUFOVF: Buffer Overflow
Reading this bit before reading the Data register will indicate the error status of the next character to be
read.
This bit is cleared by writing '1' to the bit or by disabling the receiver.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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