34.10.2. Control B
Name:
CTRLB
Offset:
0x04
Reset:
0x00000000
Property:
PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
ACKACT
CMD[1:0]
Access
R/W
R/W
R/W
Reset
0
0
0
Bit
15
14
13
12
11
10
9
8
QCEN
SMEN
Access
R
R/W
Reset
0
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
Bit 18 – ACKACT: Acknowledge Action
This bit defines the I
2
C master's acknowledge behavior after a data byte is received from the I
2
C slave.
The acknowledge action is executed when a command is written to CTRLB.CMD, or if smart mode is
enabled (CTRLB.SMEN is written to one), when DATA.DATA is read.
This bit is not enable-protected.
This bit is not write-synchronized.
Value
Description
0
Send ACK.
1
Send NACK.
Bits 17:16 – CMD[1:0]: Command
Writing these bits triggers a master operation as described below. The CMD bits are strobe bits, and
always read as zero. The acknowledge action is only valid in master read mode. In master write mode, a
command will only result in a repeated start or stop condition. The CTRLB.ACKACT bit and the CMD bits
can be written at the same time, and then the acknowledge action will be updated before the command is
triggered.
Commands can only be issued when either the Slave on Bus interrupt flag (INTFLAG.SB) or Master on
Bus interrupt flag (INTFLAG.MB) is '1'.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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