40.5.3. Clocks
The CCL bus clock (CLK_CCL_APB) can be enabled and disabled in the power manager, and the default
state of CLK_CCL_APB can be found in the
Peripheral Clock Masking
.
A generic clock (GCLK_CCL) is optionally required to clock the CCL. This clock must be configured and
enabled in the Generic Clock Controller (GCLK) before using the sequential sub-module of CCL.
GCLK_CCL is required when input events, a filter, an edge detector, or asequential sub-module is
enabled. Refer to
GCLK - Generic Clock Controller
for details.
This generic clock is asynchronous to the user interface clock (CLK_CCL_APB).
Related Links
on page 145
GCLK - Generic Clock Controller
on page 121
40.5.4. DMA
Not applicable.
40.5.5. Interrupts
Not applicable.
40.5.6. Events
The events are connected to the Event System. Refer to
EVSYS – Event System
for details on how to
configure the Event System.
Related Links
40.5.7. Debug Operation
When the CPU is halted in debug mode the CCL continues normal operation. If the CCL is configured in a
way that requires it to be periodically serviced by the CPU through interrupts or similar, improper
operation or data loss may result during debugging.
40.5.8. Register Access Protection
All registers with write-access can be write-protected optionally by the peripheral access controller (PAC).
Refer to
PAC - Peripheral Access Controller
for details.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-
Protection" property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
Related Links
PAC - Peripheral Access Controller
on page 50
40.5.9. Analog Connections
Not applicable.
40.6. Functional Description
40.6.1. Principle of Operation
Configurable Custom Logic (CCL) is a programmable logic block that can use the device port pins,
internal peripherals, and the internal Event System as both input and output channels. The CCL can
Atmel SAM L22G / L22J / L22N [DATASHEET]
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