Related Links
on page 538
33.5.2. Power Management
This peripheral can continue to operate in any sleep mode where its source clock is running. The
interrupts can wake up the device from sleep modes.
Related Links
33.5.3. Clocks
The SERCOM bus clock (CLK_SERCOMx_APB) is enabled by default, and can be enabled and disabled
in the Main Clock.
A generic clock (GCLK_SERCOMx_CORE) is required to clock the SPI. This clock must be configured
and enabled in the Generic Clock Controller before using the SPI.
This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Therefore, writes to certain
registers will require synchronization to the clock domains.
Related Links
GCLK - Generic Clock Controller
on page 121
on page 145
33.5.4. DMA
The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with
this peripheral the DMAC must be configured first. Refer to
DMAC – Direct Memory Access Controller
for
details.
Related Links
DMAC – Direct Memory Access Controller
on page 432
33.5.5. Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this
peripheral, the Interrupt Controller (NVIC) must be configured first. Refer to
Nested Vector Interrupt
Controller
for details.
Related Links
Nested Vector Interrupt Controller
on page 44
33.5.6. Events
Not applicable.
33.5.7. Debug Operation
When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is
configured to require periodical service by the CPU through interrupts or similar, improper operation or
data loss may result during debugging. This peripheral can be forced to halt operation during debugging -
refer to the Debug Control (DBGCTRL) register for details.
33.5.8. Register Access Protection
Registers with write-access can be write-protected optionally by the peripheral access controller (PAC).
PAC Write-Protection is not available for the following registers:
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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