internal memory for the active channel. For a new block transfer, the transfer descriptor will be fetched
from the descriptor memory section (
); For an ongoing block transfer, the descriptor will be
fetched from the write-back memory section (
). By using the data transfer bus, the DMAC will
read the data from the current source address and write it to the current destination address. For further
details on how the current source and destination addresses are calculated, refer to the section on
The arbitration procedure is performed after each transfer. If the current DMA channel is granted access
again, the block transfer counter (
) of the internal transfer descriptor will be decremented by the
number of beats in a transfer, the optional output event Beat will be generated if configured and enabled,
and the active channel will perform a new transfer. If a different DMA channel than the current active
channel is granted access, the block transfer counter value will be written to the write-back section before
the transfer descriptor of the newly granted DMA channel is fetched into the internal memory of the active
channel.
When a block transfer has come to its end (
is zero), the Valid bit in the Block Transfer Control
register will be cleared (
.VALID=0) before the entire transfer descriptor is written to the write-back
memory. The optional interrupts, Channel Transfer Complete and Channel Suspend, and the optional
output event Block, will be generated if configured and enabled. After the last block transfer in a
transaction, the Next Descriptor Address register (
) will hold the value 0x00000000, and the
DMA channel will either be suspended or disabled, depending on the configuration in the Block Action bit
group in the Block Transfer Control register (
.BLOCKACT). If the transaction has further block
transfers pending,
will hold the SRAM address to the next transfer descriptor to be fetched.
The DMAC will fetch the next descriptor into the internal memory of the active channel and write its
content to the write-back section for the channel, before the arbiter gets to choose the next active
channel.
26.6.2.6. Transfer Triggers and Actions
A DMA transfer through a DMA channel can be started only when a DMA transfer request is detected,
and the DMA channel has been granted access to the DMA. A transfer request can be triggered from
software, from a peripheral, or from an event. There are dedicated Trigger Source selections for each
DMA Channel Control B (CHCTRLB.TRIGSRC).
The trigger actions are available in the Trigger Action bit group in the Channel Control B register
(CHCTRLB.TRIGACT). By default, a trigger generates a request for a block transfer operation. If a single
descriptor is defined for a channel, the channel is automatically disabled when a block transfer has been
completed. If a list of linked descriptors is defined for a channel, the channel is automatically disabled
when the last descriptor in the list is executed. If the list still has descriptors to execute, the channel will
be waiting for the next block transfer trigger. When enabled again, the channel will wait for the next block
transfer trigger. The trigger actions can also be configured to generate a request for a beat transfer
(CHCTRLB.TRIGACT=0x2) or transaction transfer (CHCTRLB.TRIGACT=0x3) instead of a block transfer
(CHCTRLB.TRIGACT=0x0).
shows an example where triggers are used with two linked block descriptors.
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