has control over the output state of the pad, as well as the ability to read the current physical pad state.
Refer to
I/O Multiplexing and Considerations
for details.
Device-specific configurations may cause some lines (and the corresponding Pxy pin) not to be
implemented.
Related Links
I/O Multiplexing and Considerations
on page 27
29.5.2. Power Management
During reset, all PORT lines are configured as inputs with input buffers, output buffers and pull disabled.
If the PORT peripheral is shut down, the latches in the pad will keep their current configuration in any
sleep mode, such as the output value and pull settings. However, the PORT configuration registers and
input synchronizers will lose their contents, and these will not be restored when PORT is powered up
again. Therefore, user must reconfigure the PORT peripheral at power-up to ensure it is in a well-defined
state before use.
The PORT will continue operating in any sleep mode where the selected module source clock is running
because the selected module source clock is still running.
29.5.3. Clocks
The PORT bus clock (CLK_PORT_APB) can be enabled and disabled in the Main Clock module, and the
default state of CLK_PORT_APB can be found in the
Peripheral Clock Masking
section in
MCLK – Main
Clock
.
The PORT is fed by two different clocks: a CPU main clock, which allows the CPU to access the PORT
through the low latency CPU local bus (IOBUS); an APB clock, which is a divided clock of the CPU main
clock and allows the CPU to access the registers of PORT through the high-speed matrix and the
AHB/APB bridge.
The priority of IOBUS accesses is higher than event accesses and APB accesses. The EVSYS and APB
will insert wait states in the event of concurrent PORT accesses.
The PORT input synchronizers use the CPU main clock so that the resynchronization delay is minimized
with respect to the APB clock.
Related Links
on page 141
29.5.4. DMA
Not applicable.
29.5.5. Interrupts
Not applicable.
29.5.6. Events
The events of this peripheral are connected to the Event System.
Related Links
29.5.7. Debug Operation
When the CPU is halted in debug mode, this peripheral will continue normal operation. If the peripheral is
configured to require periodical service by the CPU through interrupts or similar, improper operation or
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