17.8.10. APBC Mask
Name:
APBCMASK
Offset:
0x1C
Reset:
0x0007 FFFF
Property:
PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
CCL
TRNG
AES
Access
R
R
R
Reset
1
1
1
Bit
15
14
13
12
11
10
9
8
SLCD
PTC
AC
ADC
TC3
TC2
TC1
TC0
Access
R/W
R/W
R/W
R/W
R
R
R
R
Reset
1
1
1
1
1
1
1
1
Bit
7
6
5
4
3
2
1
0
TCC0
SERCOM5
SERCOM4
SERCOM3
SERCOM2
SERCOM1
SERCOM0
EVSYS
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
Bit 18 – CCL: CCL APBC Clock Enable
Value
Description
0
The APBC clock for the CCL is stopped.
1
The APBC clock for the CCL is enabled.
Bit 17 – TRNG: TRNG APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TRNG is stopped.
1
The APBC clock for the TRNG is enabled.
Bit 16 – AES: AES APBC Mask Clock Enable
Value
Description
0
The APBC clock for the AES is stopped.
1
The APBC clock for the AES is enabled.
Bit 15 – SLCD: SLCD APBC Clock Enable
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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