Atmel ATSAML22G16A-AUT, Manual

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Number of
Accumulated
Samples AVGCTRL.
SAMPLENUM Intermediate
Result
Precision Number of
Automatic
Right
Shifts Division
Factor AVGCTRL.ADJRES Total
Number
of Right
Shifts
Final
Result
Precision Automatic
Division
Factor
64 0x6 18 2 16 0x4 6 12 bits 4
128 0x7 19 3 16 0x4 7 12 bits 8
256 0x8 20 4 16 0x4 8 12 bits 16
512 0x9 21 5 16 0x4 9 12 bits 32
1024 0xA 22 6 16 0x4 10 12 bits 64
Reserved 0xB –0xF 0x0 12 bits 0
41.6.2.11. Oversampling and Decimation
By using oversampling and decimation, the ADC resolution can be increased from 12 bits up to 16 bits,
for the cost of reduced effective sampling rate.
To increase the resolution by n bits, 4
n
samples must be accumulated. The result must then be right-
shifted by n bits. This right-shift is a combination of the automatic right-shift and the value written to
AVGCTRL.ADJRES. To obtain the correct resolution, the ADJRES must be configured as described in the
table below. This method will result in n bit extra LSB resolution.
Table 41-3. Configuration Required for Oversampling and Decimation
Result
Resolution Number of
Samples to
Average AVGCTRL.SAMPLENUM[3:0] Number of
Automatic
Right Shifts
AVGCTRL.ADJRES[2:0]
13 bits 4
1
= 4 0x2 0 0x1
14 bits 4
2
= 16 0x4 0 0x2
15 bits 4
3
= 64 0x6 2 0x1
16 bits 4
4
= 256 0x8 4 0x0
41.6.2.12. Automatic Sequences
The ADC has the ability to automatically sequence a series of conversions. This means that each time
the ADC receives a start-of-conversion request, it can perform multiple conversions automatically. All of
the 32 positive inputs can be included in a sequence by writing to corresponding bits in the Sequence
Control register (SEQCTRL). The order of the conversion in a sequence is the lower positive MUX
selection to upper positive MUX (AIN0, AIN1, AIN2 ...). In differential mode, the negative inputs selected
by MUXNEG field, will be used for the entire sequence.
When a sequence starts, the Sequence Busy status bit in Sequence Status register
(SEQSTATUS.SEQBUSY) will be set. When the sequence is complete, the Sequence Busy status bit will
be cleared.
Each time a conversion is completed, the Sequence State bit in Sequence Status register
(SEQSTATUS.SEQSTATE) will store the input number from which the conversion is done. The result will
be stored in the RESULT register, and the Result Ready Interrupt Flag (INTFLAG.RESRDY) is set.
If additional inputs must be scanned, the ADC will automatically start a new conversion on the next input
present in the sequence list.
Note that if SEQCTRL register has no bits set to '1', the conversion is done with the selected MUXPOS
input.
Atmel SAM L22G / L22J / L22N [DATASHEET]
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