Atmel ATSAML22G16A-AUT, Manual

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The pattern generator unit produces a synchronized bit pattern across the port pins it is connected to.
The pattern generation features are primarily intended for handling the commutation sequence in
brushless DC motors (BLDC), stepper motors, and full bridge control. See also
Figure 36-35 .
Figure 36-35. Pattern Generator Block Diagram
COUNT
UPDATE
BV BV PGEB[7:0]
PGE[7:0]
PGVB[7:0]
PGV[7:0]
SWAP output
EN EN
WOx[7:0]
As with other double-buffered timer/counter registers, the register update is synchronized to the UPDATE
condition set by the timer/counter waveform generation operation. If synchronization is not required by the
application, the software can simply access directly the PATT.PGE, PATT.PGV bits registers.
36.6.4. DMA, Interrupts, and Events
Table 36-6. Module Requests for TCC
Condition Interrupt
request Event
output Event
input DMA
request DMA request is
cleared
Overflow / Underflow Yes Yes Yes
(1)
On DMA acknowledge
Channel Compare
Match or Capture Yes Yes Yes
(2)
Yes
(3)
For circular buffering:
on DMA acknowledge
For capture channel:
when CCx register is
read
Retrigger Yes Yes
Count Yes Yes
Capture Overflow Error Yes
Debug Fault State Yes
Recoverable Faults Yes
Non-Recoverable Faults Yes
TCCx Event 0 input Yes
(4)
TCCx Event 1 input Yes
(5)
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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