•
Data Ready (DRDY)
•
Address Match (AMATCH)
•
Stop Received (PREC)
The I
2
C master has the following interrupt sources. These are asynchronous interrupts. They can wake-
up the device from any sleep mode:
•
Error (ERROR)
•
Slave on Bus (SB)
•
Master on Bus (MB)
Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) will be set when the interrupt condition is meet. Each interrupt can be individually
enabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Set register (INTENSET), and
disabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An
interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request active until the interrupt flag is cleared, the interrupt is disabled or the I
2
C is reset.
register for details on how to clear interrupt flags.
The I
2
C has one common interrupt request line for all the interrupt sources. The value of INTFLAG
indicates which interrupt is executed. Note that interrupts must be globally enabled for interrupt requests.
Refer to
Nested Vector Interrupt Controller
for details.
Related Links
Nested Vector Interrupt Controller
on page 44
34.6.4.3. Events
Not applicable.
34.6.5. Sleep Mode Operation
I
2
C Master Operation
The generic clock (GCLK_SERCOMx_CORE) will continue to run in idle sleep mode. If the Run In
Standby bit in the Control A register (CTRLA.RUNSTDBY) is '1', the GLK_SERCOMx_CORE will also run
in standby sleep mode. Any interrupt can wake up the device.
If CTRLA.RUNSTDBY=0, the GLK_SERCOMx_CORE will be disabled after any ongoing transaction is
finished. Any interrupt can wake up the device.
I
2
C Slave Operation
Writing CTRLA.RUNSTDBY=1 will allow the Address Match interrupt to wake up the device.
When CTRLA.RUNSTDBY=0, all receptions will be dropped.
34.6.6. Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
The following bits are synchronized when written:
•
Software Reset bit in the CTRLA register (CTRLA.SWRST)
•
Enable bit in the CTRLA register (CTRLA.ENABLE)
•
Write to Bus State bits in the Status register (STATUS.BUSSTATE)
•
Address bits in the Address register (ADDR.ADDR) when in master operation.
The following registers are synchronized when written:
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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