27.4. Signal Description
Signal Name
Type
Description
EXTINT[15..0]
Digital Input
External interrupt pin
NMI
Digital Input
Non-maskable interrupt pin
One signal can be mapped on several pins.
27.5. Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
27.5.1. I/O Lines
Using the EIC’s I/O lines requires the I/O pins to be configured.
Related Links
on page 538
27.5.2. Power Management
All interrupts are available in all sleep modes, but the EIC can be configured to automatically mask some
interrupts in order to prevent device wake-up.
The EIC will continue to operate in any sleep mode where the selected source clock is running. The EIC’s
interrupts can be used to wake up the device from sleep modes. Events connected to the Event System
can trigger other operations in the system without exiting sleep modes.
Related Links
27.5.3. Clocks
The EIC bus clock (CLK_EIC_APB) can be enabled and disabled by the Main Clock Controller, the
default state of CLK_EIC_APB can be found in the Peripheral Clock Masking section.
Some optional functions need a peripheral clock, which can either be a generic clock (GCLK_EIC, for
wider frequency selection) or a Ultra Low Power 32KHz clock (CLK_ULP32K, for highest power
efficiency). One of the clock sources must be configured and enabled before using the peripheral:
GCLK_EIC is configured and enabled in the Generic Clock Controller.
CLK_ULP32K is provided by the internal ultra-low-power (OSCULP32K) oscillator in the OSC32KCTRL
module.
Both GCLK_EIC and CLK_ULP32K are asynchronous to the user interface clock (CLK_EIC_APB). Due
to this asynchronicity, writes to certain registers will require synchronization between the clock domains.
Refer to
Related Links
on page 141
on page 145
GCLK - Generic Clock Controller
on page 121
OSC32KCTRL – 32KHz Oscillators Controller
on page 258
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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