CCx/CCBUFx registers will generate a PAC error, and access to the respective PER or CCx register is
invalid.
When the buffer valid flag bit in the STATUS register is '1' and the Lock Update bit in the CTRLB register
is set to '0', (writing CTRLBCLR.LUPD to '1'), double buffering is enabled: the data from buffer registers
will be copied into the corresponding register under hardware UPDATE conditions, then the buffer valid
flags bit in the STATUS register are automatically cleared by hardware.
Note:
The software update command (CTRLBSET.CMD=0x3) is acting independently of the LUPD
value.
A compare register is double buffered as in the following figure.
Figure 35-7. Compare Channel Double Buffering
CCBUFVx
UPDATE
"write enable"
"data write"
=
COUNT
"match"
EN
EN
CCBUFx
CCx
Both the registers (PER/CCx) and corresponding buffer registers (PERBUF/CCBUFx) are available in the
I/O register map, and the double buffering feature is not mandatory. The double buffering is disabled by
writing a '1' to CTRLBSET.LUPD.
Note: In NFRQ, MFRQ or PWM down-counting counter mode (CTRLBSET.DIR=1), when double buffering
is enabled (CTRLBCLR.LUPD=1), PERBUF register is continously copied into the PER independently of
update conditions.
Changing the Period
The counter period can be changed by writing a new TOP value to the Period register (PER or CC0,
depending on the waveform generation mode), any period update on registers (PER or CCx) is effective
after the synchronization delay, whatever double buffering enabling is.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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