33.8.6. Interrupt Flag Status and Clear
Name:
INTFLAG
Offset:
0x18
Reset:
0x00
Property:
-
Bit
7
6
5
4
3
2
1
0
ERROR
SSL
RXC
TXC
DRE
Access
R/W
R/W
R
R/W
R
Reset
0
0
0
0
0
Bit 7 – ERROR: Error
This flag is cleared by writing '1' to it.
This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in
the STATUS register. The BUFOVF error will set this interrupt flag.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 3 – SSL: Slave Select Low
This flag is cleared by writing '1' to it.
This bit is set when a high to low transition is detected on the _SS pin in slave mode and Slave Select
Low Detect (CTRLB.SSDE) is enabled.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 2 – RXC: Receive Complete
This flag is cleared by reading the Data (DATA) register or by disabling the receiver.
This flag is set when there are unread data in the receive buffer. If address matching is enabled, the first
data received in a transaction will be an address.
Writing '0' to this bit has no effect.
Writing '1' to this bit has no effect.
Bit 1 – TXC: Transmit Complete
This flag is cleared by writing '1' to it or by writing new data to DATA.
In master mode, this flag is set when the data have been shifted out and there are no new data in DATA.
In slave mode, this flag is set when the _SS pin is pulled high. If address matching is enabled, this flag is
only set if the transaction was initiated with an address match.
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the flag.
Bit 0 – DRE: Data Register Empty
This flag is cleared by writing new data to DATA.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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