Atmel ATSAML22G16A-AUT, Manual

Page: 453 / 1231

CRC on
DMA
data CRC-16 or CRC-32 calculations can be performed on data passing through any DMA
channel. Once a DMA channel is selected as the source, the CRC engine will continuously
generate the CRC on the data passing through the DMA channel. The checksum is available
for readout once the DMA transaction is completed or aborted. A CRC can also be generated
on SRAM, Flash, or I/O memory by passing these data through a DMA channel. If the latter is
done, the destination register for the DMA data can be the data input (
CRCDATAIN ) register in
the CRC engine.
CRC using the I/O
interface Before using the CRC engine with the I/O interface, the application must set the
CRC Beat Size bits in the CRC Control register (
CRCCTRL .CRCBEATSIZE).
8/16/32-bit bus transfer type can be selected.
CRC can be performed on any data by loading them into the CRC engine using the CPU and writing the
data to the
CRCDATAIN register. Using this method, an arbitrary number of bytes can be written to the
register by the CPU, and CRC is done continuously for each byte. This means if a 32-bit data is written to
the
CRCDATAIN register the CRC engine takes four cycles to calculate the CRC. The CRC complete is
signaled by a set CRCBUSY bit in the CRCSTATUS register. New data can be written only when
CRCBUSY flag is not set.
26.6.4. DMA Operation
Not applicable.
26.6.5. Interrupts
The DMAC channels have the following interrupt sources:
• Transfer Complete (TCMPL): Indicates that a block transfer is completed on the corresponding
channel. Refer to
Data Transmission for details.
• Transfer Error (TERR): Indicates that a bus error has occurred during a burst transfer, or that an
invalid descriptor has been fetched. Refer to
Error Handling for details.
• Channel Suspend (SUSP): Indicates that the corresponding channel has been suspended. Refer to
Channel Suspend and Data Transmission for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Channel Interrupt
Flag Status and Clear (
CHINTFLAG ) register is set when the interrupt condition occurs. Each interrupt
can be individually enabled by setting the corresponding bit in the Channel Interrupt Enable Set register
(
CHINTENSET =1), and disabled by setting the corresponding bit in the Channel Interrupt Enable Clear
register ( CHINTENCLR =1).
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, the DMAC
is reset or the corresponding DMA channel is reset. See
CHINTFLAG for details on how to clear interrupt
flags. All interrupt requests are ORed together on system level to generate one combined interrupt
request to the NVIC.
The user must read the Channel Interrupt Status ( INTSTATUS ) register to identify the channels with
pending interrupts and must read the Channel Interrupt Flag Status and Clear ( CHINTFLAG ) register to
determine which interrupt condition is present for the corresponding channel. It is also possible to read
the Interrupt Pending register (
INTPEND ), which provides the lowest channel number with pending
interrupt and the respective interrupt flags.
Note: Interrupts must be globally enabled for interrupt requests to be generated.
Related Links
Nested Vector Interrupt Controller on page 44
Atmel SAM L22G / L22J / L22N [DATASHEET]
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