39.8.3.7. Device Interrupt EndPoint Set n
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENCLR) register. This
register is cleared by USB reset or when EPEN[n] is zero.
Name:
EPINTENSETn
Offset:
0x109 + (n x 0x20)
Reset:
0x0000
Property:
PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
STALL1
STALL0
RXSTP
TRFAIL1
TRFAIL0
TRCPT1
TRCPT0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Bit 6 – STALL1: Transmit Stall 1 Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transmit bank 1 Stall interrupt.
Value
Description
0
The Transmit Stall 1 interrupt is disabled.
1
The Transmit Stall 1 interrupt is enabled.
Bit 5 – STALL0: Transmit Stall 0 Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transmit bank 0 Stall interrupt.
Value
Description
0
The Transmit Stall 0 interrupt is disabled.
1
The Transmit Stall 0 interrupt is enabled.
Bit 4 – RXSTP: Received Setup Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Received Setup interrupt.
Value
Description
0
The Received Setup interrupt is disabled.
1
The Received Setup interrupt is enabled.
Bit 3 – TRFAIL1: Transfer Fail bank 1 Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Fail interrupt.
Value
Description
0
The Transfer Fail interrupt is disabled.
1
The Transfer Fail interrupt is enabled.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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