21.6.3. Clock Failure Detection Operation
The Clock Failure Detector (CFD) allows the user to monitor the external clock or crystal oscillator signal
provided by the external oscillator (XOSC). The CFD detects failing operation of the XOSC clock with
reduced latency, and allows to switch to a safe clock source in case of clock failure. The user can also
switch from the safe clock back to XOSC in case of recovery. The safe clock is derived from the OSC16M
oscillator with a configurable prescaler. This allows to configure the safe clock in order to fulfill the
operative conditions of the microcontroller.
In sleep modes, CFD operation is automatically disabled when the external oscillator is not requested to
run by a peripheral. See the Sleep Behavior table above when this is the case.
The user interface registers allow to enable, disable, and configure the CFD. The Status register provides
status flags on failure and clock switch conditions. The CFD can optionally trigger an interrupt or an event
when a failure is detected.
Clock Failure Detection
The CFD is reset only at power-on (POR). The CFD does not monitor the XOSC clock when the oscillator
is disabled (XOSCCTRL.ENABLE=0).
Before starting CFD operation, the user must start and enable the safe clock source (OSC16M oscillator).
CFD operation is started by writing a '1' to the CFD Enable bit in the External Oscillator Control register
(XOCCTRL.CFDEN). After starting or restarting the XOSC, the CFD does not detect failure until the start-
up time has elapsed. The start-up time is configured by the Oscillator Start-Up Time in the External
Multipurpose Crystal Oscillator Control register (XOSCCTRL.STARTUP). Once the XOSC Start-Up Time
is elapsed, the XOSC clock is constantly monitored.
During a period of 4 safe clocks (monitor period), the CFD watches for a clock activity from the XOSC.
There must be at least one rising and one falling XOSC clock edge during 4 safe clock periods to meet
non-failure conditions. If no or insufficient activity is detected, the failure status is asserted: The Clock
Failure Detector status bit in the Status register (STATUS.CLKFAIL) and the Clock Failure Detector
interrupt flag bit in the Interrupt Flag register (INTFLAG.CLKFAIL) are set. If the CLKFAIL bit in the
Interrupt Enable Set register (INTENSET.CLKFAIL) is set, an interrupt is generated as well. If the Event
Output enable bit in the Event Control register (EVCTRL.CFDEO) is set, an output event is generated,
too.
After a clock failure was issued the monitoring of the XOSC clock is continued, and the Clock Failure
Detector status bit in the Status register (STATUS.CLKFAIL) reflects the current XOSC activity.
Clock Switch
When a clock failure is detected, the XOSC clock is replaced by the safe clock in order to maintain an
active clock during the XOSC clock failure. The safe clock source is the OSC16M oscillator clock. The
safe clock source can be scaled down by a configurable prescaler to ensure that the safe clock frequency
does not exceed the operating conditions selected by the application. When the XOSC clock is switched
to the safe clock, the Clock Switch bit in the Status register (STATUS.CLKSW) is set.
When the CFD has switched to the safe clock, the XOSC is not disabled. If desired, the application must
take the necessary actions to disable the oscillator. The application must also take the necessary actions
to configure the system clocks to continue normal operations.
In the case the application can recover the XOSC, the application can switch back to the XOSC clock by
writing a '1' to Switch Back Enable bit in the Clock Failure Control register (XOSCCTRL.SWBACK). Once
the XOSC clock is switched back, the Switch Back bit (XOSCCTRL.SWBACK) is cleared by hardware.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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