Frequency Error Measurement
The ratio between CLK_DFLL48M_REF and CLK48M_DFLL is measured automatically when the
DFLL48M is in closed-loop mode. The difference between this ratio and the value in DFLLMUL.MUL is
stored in the DFLL Multiplication Ratio Difference bit group (DFLLVAL.DIFF) in the DFLL Value register.
The relative error of CLK_DFLL48M with respect to the target frequency is calculated as follows:
����� = DFLLVAL.DIFF
DFLLMUL.MUL
Drift Compensation
If the Stable DFLL Frequency bit (DFLLCTRL.STABLE) in the DFLL Control register is '0', the frequency
tuner will automatically compensate for drift in the CLK_DFLL48M without losing either of the locks.
Note:
This means that DFLLVAL.FINE can change after every measurement of CLK_DFLL48M.
The DFLLVAL.FINE value may overflow or underflow in closed-loop mode due to large drift/instability of
the clock source reference, and the DFLL Out Of Bounds bit (STATUS.DFLLOOB) in the Status register
will be set. After an Out of Bounds error condition, the user must rewrite DFLLMUL.MUL to ensure correct
CLK_DFLL48M frequency.
A zero-to-one transition of STATUS.DFLLOOB will generate an interrupt, if the DFLL Out Of Bounds bit in
the Interrupt Enable Set register (INTENSET.DFLLOOB) is '1'. This interrupt will also be set if the tuner is
not able to lock on the correct Coarse value.
To avoid this out-of-bounds error, the reference clock must be stable; an external oscillator XOSC32K is
recommended.
Reference Clock Stop Detection
If CLK_DFLL48M_REF stops or is running at a very low frequency (slower than CLK_DFLL48M/(2 *
MUL
MAX
)), the DFLL Reference Clock Stopped bit in the Status register (STATUS.DFLLRCS) will be set.
Detecting a stopped reference clock can take a long time, in the order of 217 CLK_DFLL48M cycles.
When the reference clock is stopped, the DFLL48M will operate as if in open-loop mode. Closed-loop
mode operation will automatically resume when the CLK_DFLL48M_REF is restarted.
A zero-to-one transition of the DFLL Reference Clock Stopped bit in the Status register
(STATUS.DFLLRCS) will generate an interrupt, if the DFLL Reference Clock Stopped bit in the Interrupt
Enable Set register (INTENSET.DFLLRCS) is '1'.
21.6.5.2. Additional Features
Dealing with Settling Time in Closed-Loop Mode
The time from selecting a new CLK_DFLL48M output frequency until this frequency is output by the
DFLL48M can be up to several microseconds. A small value in DFLLMUL.MUL can lead to instability in
the DFLL48M locking mechanism, which can prevent the DFLL48M from achieving locks.
To avoid this, a chill cycle can be enabled, during which the CLK_DFLL48M frequency is not measured.
The chill cycle is enabled by default, but can be disabled by writing '1' to the DFLL Chill Cycle Disable bit
in the DFLL Control register (DFLLCTRL.CCDIS). Enabling chill cycles might double the lock time.
Another solution to this problem is using less strict lock requirements. This is called Quick Lock (QL). QL
is enabled by default as well, but it can be disabled by writing '1' to the Quick Lock Disable bit in the DFLL
Control register (DFLLCTRL.QLDIS). The Quick Lock might lead to a larger spread in the output
frequency than chill cycles, but the average output frequency is the same.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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