Writing a '0' to the CTRL.SWRST bit has no effect.
The Ready interrupt (if available) cannot be used for Software Reset write-synchronization.
15.3.7. Synchronization Delay
The synchronization will delay write and read accesses by a certain amount. This delay
D
is within the
range of:
5×P
GCLK
+ 2×P
APB
< D < 6×P
GCLK
+ 3×P
APB
Where P
GCLK
is the period of the generic clock and P
APB
is the period of the peripheral bus clock. A
normal peripheral bus register access duration is 2×P
APB
.
15.4. Enabling a Peripheral
In order to enable a peripheral that is clocked by a Generic Clock, the following parts of the system needs
to be configured:
•
A running Clock Source
•
A clock from the Generic Clock Generator must be configured to use one of the running Clock
Sources, and the Generator must be enabled.
•
The Peripheral Channel that provides the Generic Clock signal to the peripheral must be configured
to use a running Generic Clock Generator, and the Generic Clock must be enabled.
•
The user interface of the peripheral needs to be unmasked in the PM. If this is not done the
peripheral registers will read all 0’s and any writing attempts to the peripheral will be discarded.
15.5. On Demand Clock Requests
Figure 15-4. Clock Request Routing
DFLL48M
Generic Clock
Generator
Clock request
Generic Clock
Periph. Channel
Clock request
Peripheral
Clock request
ENABLE
RUNSTDBY
ONDEMAND
CLKEN
RUNSTDBY
ENABLE
RUNSTDBY
GENEN
All clock sources in the system can be run in an on-demand mode: the clock source is in a stopped state
unless a peripheral is requesting the clock source. Clock requests propagate from the peripheral, via the
GCLK, to the clock source. If one or more peripheral is using a clock source, the clock source will be
started/kept running. As soon as the clock source is no longer needed and no peripheral has an active
request, the clock source will be stopped until requested again.
The clock request can reach the clock source only if the peripheral, the generic clock and the clock from
the Generic Clock Generator in-between are enabled. The time taken from a clock request being asserted
to the clock source being ready is dependent on the clock source startup time, clock source frequency as
well as the divider used in the Generic Clock Generator. The total startup time T
start
from a clock request
until the clock is available for the peripheral is between:
T
start_max
= Clock source startup time + 2 × clock source p 2 × divided clock source periods
T
start_min
= Clock source startup time + 1 × clock source 1 × divided clock source period
The time between the last active clock request stopped and the clock is shut down, T
stop
, is between:
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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