25.10.4. Interrupt Enable Clear in COUNT16 mode (CTRLA.MODE=1)
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name:
INTENCLR
Offset:
0x08
Reset:
0x0000
Property:
PAC Write-Protection
Bit
15
14
13
12
11
10
9
8
OVF
TAMPER
CMP1
CMP0
Access
R/W
R/W
R/W
R/W
Reset
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PER7
PER6
PER5
PER4
PER3
PER2
PER1
PER0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit 15 – OVF: Overflow Interrupt Enable
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Overflow Interrupt Enable bit,
which disables the Overflow interrupt.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
Bit 14 – TAMPER: Tamper Interrupt Enable
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Tamper Interrupt Enable bit, which
disables the Tamper interrupt.
Value
Description
0
The Tamper interrupt is disabled.
1
The Tamper interrupt is enabled.
Bits 9:8 – CMPn: Compare n Interrupt Enable [n = 1..0]
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Compare n Interrupt Enable bit,
which disables the Compare n interrupt.
Value
Description
0
The Compare n interrupt is disabled.
1
The Compare n interrupt is enabled.
Bits 7:0 – PERn: Periodic Interval n Interrupt Enable [n = 7..0]
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Periodic Interval n Interrupt
Enable bit, which disables the Periodic Interval n interrupt.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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