36.8.11. Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name:
INTENSET
Offset:
0x28
Reset:
0x000000
Property:
PAC Write-Protection
Bit
23
22
21
20
19
18
17
16
MC3
MC2
MC1
MC0
Access
R/W
R/W
R/W
R/W
Reset
0
0
0
0
Bit
15
14
13
12
11
10
9
8
FAULT1
FAULT0
FAULTB
FAULTA
DFS
Access
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ERR
CNT
TRG
OVF
Access
R/W
R/W
R/W
R/W
Reset
0
0
0
0
Bit 13 – FAULTB: Recoverable Fault B Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Recoverable Fault B Interrupt Disable/Enable bit, which enables the
Recoverable Fault B interrupt.
Value
Description
0
The Recoverable Fault B interrupt is disabled.
1
The Recoverable Fault B interrupt is enabled.
Bit 12 – FAULTA: Recoverable Fault A Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Recoverable Fault A Interrupt Disable/Enable bit, which enables the
Recoverable Fault A interrupt.
Value
Description
0
The Recoverable Fault A interrupt is disabled.
1
The Recoverable Fault A interrupt is enabled.
Bit 11 – DFS: Debug Fault State Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Debug Fault State Interrupt Disable/Enable bit, which enables the
Debug Fault State interrupt.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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